Dma Register Map; Table 50. Dma Register Map And Reset Values - ST STM32G0 1 Series Reference Manual

RM0444
Bits 31:0 MA[31:0]: peripheral address
It contains the base address of the memory from/to which the data will be read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: this register is set and cleared by software.
10.6.7

DMA register map

The table below gives the DMA register map and reset values.
Offset Register
DMA_ISR
0x000
Reset value
DMA_IFCR
0x004
Reset value
DMA_CCR1
0x008
Reset value
DMA_CNDTR1
0x00C
Reset value
DMA_CPAR1
0x010
Reset value
DMA_CMAR1
0x014
Reset value
0x018 Reserved
DMA_CCR2
0x01C
Reset value
DMA_CNDTR2
0x020
Reset value
DMA_CPAR2
0x024
Reset value
DMA_CMAR2
0x028
Reset value
0x02C Reserved
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

Table 50. DMA register map and reset values

0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Direct memory access controller (DMA)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0
PA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved.
0
PA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved.
RM0444 Rev 5
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
NDTR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
NDTR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
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