Ucpd Rx Ordered Set Extension Register 1; (Ucpd_Rx_Ordextr1); (Ucpd_Rx_Ordextr2) - ST STM32G0 1 Series Reference Manual

USB Type-C™ / USB Power Delivery interface (UCPD)
38.7.14

UCPD Rx ordered set extension register 1

(UCPD_RX_ORDEXTR1)

Address offset: 0x034
Reset value: 0x0000 0000
Writing to this register is only effective when the peripheral is disabled (UCPDEN = 0).
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 RXSOPX1[19:0]: Ordered set 1 received
The bitfield contains a full 20-bit sequence received, consisting of four K-codes, each of five
bits. The bit 0 (bit 0 of K-code1) is receive first, the bit 19 (bit 4 of K-code4) last.
38.7.15 UCPD Rx ordered set extension register 2

(UCPD_RX_ORDEXTR2)

Address offset: 0x038
Reset value: 0x0000 0000
Writing to this register is only effective when the peripheral is disabled (UCPDEN = 0).
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 RXSOPX2[19:0]: Ordered set 2 received
The bitfield contains a full 20-bit sequence received, consisting of four K-codes, each of five
bits. The bit 0 (bit 0 of K-code1) is receive first, the bit 19 (bit 4 of K-code4) last.
1344/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
RXSOPX1[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
RXSOPX2[15:0]
rw rw rw
RM0444 Rev 5
21 20 19 18
Res. Res. RXSOPX1[19:16]
rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. RXSOPX2[19:16]
rw rw
5 4 3 2
rw rw rw rw
RM0444
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw