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RM0444
Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
20.7.13
AES key register 4 (AES_KEYR4)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
20.7.14
AES key register 5 (AES_KEYR5)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0 KEY[191:160]: Cryptographic key, bits [191:160]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
20.7.15
AES key register 6 (AES_KEYR6)
Address offset: 0x38
Reset value: 0x0000 0000
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0 KEY[223:192]: Cryptographic key, bits [223:192]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
24
23
22
KEY[159:144]
w
w
w
8
7
6
KEY[143:128]
w
w
w
24
23
22
KEY[191:176]
w
w
w
8
7
6
KEY[175:160]
w
w
w
24
23
22
KEY[223:208]
w
w
w
8
7
6
KEY[207:192]
w
w
w
RM0444 Rev 5
AES hardware accelerator (AES)
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
17
16
w
w
1
0
w
w
17
16
w
w
1
0
w
w
17
16
w
w
1
0
w
w
519/1390
522
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