Ucpd Rx Ordered Set Register (Ucpd_Rx_Ordsetr) - ST STM32G0 1 Series Reference Manual

USB Type-C™ / USB Power Delivery interface (UCPD)
38.7.11

UCPD Rx ordered set register (UCPD_RX_ORDSETR)

Address offset: 0x028
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bits 6:4 RXSOPKINVALID[2:0]:
The bitfield is for debug purposes only.
0x0: No K-code corrupted
0x1: First K-code corrupted
0x2: Second K-code corrupted
0x3: Third K-code corrupted
0x4: Fourth K-code corrupted
Others: Invalid
Bit 3 RXSOP3OF4:
The bit indicates the number of correct K-codes. For debug purposes only.
0: 4 correct K-codes out of 4
1: 3 correct K-codes out of 4
Bits 2:0 RXORDSET[2:0]: Rx ordered set code detected
0x0: SOP code detected in receiver
0x1: SOP' code detected in receiver
0x2: SOP'' code detected in receiver
0x3: SOP'_Debug detected in receiver
0x4: SOP''_Debug detected in receiver
0x5: Cable Reset detected in receiver
0x6: SOP extension#1 detected in receiver
0x7: SOP extension#2 detected in receiver
1342/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
r
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
RM0444
17 16
Res. Res.
1 0
RXORDSET[2:0]
r r