Fdcan Tx Fifo/Queue Status Register (Fdcan_Txfqs) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TFQM: Tx FIFO/queue mode
0: Tx FIFO operation
1: Tx queue operation.
This is a protected write (P) bit, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bits 23:0 Reserved, must be kept at reset value.
36.4.27

FDCAN Tx FIFO/queue status register (FDCAN_TXFQS)

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP.
Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan
(TXBRP not yet updated).
Address offset: 0x00C4
Reset value: 0x0000 0003
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 TFQF: Tx FIFO/queue full
0: Tx FIFO/queue not full
1: Tx FIFO/queue full
Bits 20:18 Reserved, must be kept at reset value.
Bits 17:16 TFQPI[1:0]: Tx FIFO/queue put index
Tx FIFO/queue write index pointer, range 0 to 3
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 TFGI[1:0]: Tx FIFO get index
Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx queue operation is configured
(TXBC.TFQM = 1)
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 TFFL[2:0]: Tx FIFO free level
Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0
when Tx queue operation is configured (TXBC[TFQM] = 1).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. TFGI[1:0]
r
FD controller area network (FDCAN)
24 23 22
Res. Res. Res. TFQF
8 7 6
Res. Res.
r
RM0444 Rev 5
21 20 19 18
Res. Res. Res.
r
5 4 3 2
Res. Res. Res.
r
17 16
TFQPI[1:0]
r r
1 0
TFFL[2:0]
r r
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