Table 203. Dlc Coding In Fdcan - ST STM32G0 1 Series Reference Manual

FD controller area network (FDCAN)
A mode change during CAN operation is recommended only under the following conditions:
•
The failure rate in the CAN FD data phase is significant higher than in the CAN FD
arbitration phase. In this case disable the CAN FD bit rate switching option for
transmissions.
• During system startup all nodes are transmitting Classic CAN messages until it is
verified that they are able to communicate in CAN FD format. If this is true, all nodes
switch to CAN FD operation.
•
Wake-up messages in CAN Partial Networking have to be transmitted in Classic CAN
format.
•
End-of-line programming in case not all nodes are CAN FD capable. Non CAN FD
nodes are held in Silent mode until programming is completed. Then all nodes switch
back to Classic CAN communication.
In the FDCAN format, the coding of the DLC differs from the one of the standard CAN
format. The DLC codes 0 to 8 have the same coding as in standard CAN, the codes 9 to 15
(that in standard CAN all code a data field of 8 bytes) are coded according to
:
Number of data bytes
In CAN FD Fast Frames, the bit timing is switched inside the frame, after the BRS (Bit Rate
Switch) bit, if this bit is recessive. Before the BRS bit, in the FDCAN arbitration phase, the
standard CAN bit timing is used as defined by the Bit Timing and Prescaler register BTP. In
the following FDCAN data phase, the fast CAN bit timing is used as defined by the Fast Bit
Timing and Prescaler register FBTP. The bit timing is switched back from the fast timing at
the CRC delimiter or when an error is detected, whichever occurs first.
The maximum configurable bit rate in the CAN FD data phase depends on the FDCAN
kernel clock frequency. For example, with a FDCAN kernel clock frequency of 20 MHz and
the shortest configurable bit time of four time quanta (tq), the bit rate in the data phase is
5 Mbit/s.
In both data frame formats, CAN FD Long Frames and CAN FD Fast Frames, the value of
the bit ESI (Error Status Indicator) is determined by the transmitter error state at the start of
the transmission. If the transmitter is error passive, ESI is transmitted recessive, else it is
transmitted dominant. In CAN FD remote frames the ESI bit is always transmitted dominant,
independent of the transmitter error state. The data length code of CAN FD remote frames
is transmitted as 0.
In case a FDCAN Tx Buffer is configured for FDCAN transmission with DLC > 8, the first 8
bytes are transmitted as configured in the Tx Buffer while the remaining part of the data field
is padded with 0xCC. When the FDCAN receives a FDCAN frame with DLC > 8, the first 8
bytes of that frame are stored into the matching Rx FIFO. The remaining bytes are
discarded.
Transceiver delay compensation
During the data phase of a FDCAN transmission only one node is transmitting, all others are
receivers. The length of the bus line has no impact. When transmitting via pin FDCAN_TX
the protocol controller receives the transmitted data from its local CAN transceiver via pin
FDCAN_RX. The received data is delayed by the CAN transceiver loop delay. In case this
1204/1390

Table 203. DLC coding in FDCAN

DLC 9
12
10 11
16 20
RM0444 Rev 5
12 13 14
24 32 48
RM0444
Table 203.
15
64