Usb And Usb Sram Registers; Common Registers - ST STM32G0 1 Series Reference Manual

RM0444
37.6

USB and USB SRAM registers

The USB peripheral registers can be divided into the following groups:
•
Common registers: interrupt and control registers
• endpoint/channel registers: endpoint/channel configuration and status
The USB SRAM registers cover:
•
Buffer descriptor table: location of packet memory used to locate data buffers (see
Section 2.2: Memory organization
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address, except the buffer descriptor table locations, which starts at the USB SRAM
base address.
Refer to
The peripheral registers can be accessed by words (32-bit).
37.6.1

Common registers

These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0000 0003
31 30 29
HOST Res. Res. Res.
rw
15 14 13
PMA WKUP
CTRM ERRM
OVRM
rw rw rw
Bit 31 HOST: HOST mode
Bits 30:17 Reserved, must be kept at reset value.
Bit 16 THR512M: 512 byte threshold interrupt mask
Bit 15 CTRM: Correct transfer interrupt mask
Universal serial bus full-speed host/device interface (USB)
Section 1.2 on page 53
28 27 26 25
Res. Res. Res.
12 11 10 9
SUSP RST_D
SOFM
M M CONM
rw rw rw rw
HOST bit selects betweens host or device USB mode of operation. It must be set before
enabling the USB peripheral by the function enable bit.
0: USB Device function
1: USB host function
0: 512 byte threshold interrupt disabled
1: 512 byte threshold interrupt enabled
0: Correct transfer (CTR) interrupt disabled.
1: CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
to find USB SRAM base address).
for a list of abbreviations used in register descriptions.
24 23 22
Res. Res. Res.
8 7 6
ESOF L1REQ L1RE
Res.
M M
rw rw
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
L2RE SUS SUSP
S S PEN RDY
rw rw rw r
17 16
THR
Res.
512M
rw
1 0
USB
PDWN
RST
rw rw
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