Tim15 Capture/Compare Enable Register (Tim15_Ccer) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 3 OC1PE: Output Compare 1 preload enable
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
Bit 2 OC1FE: Output Compare 1 fast enable
Bits 1:0 CC1S[1:0]: Capture/Compare 1 selection
Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
25.5.9

TIM15 capture/compare enable register (TIM15_CCER)

Address offset: 0x20
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
Refer to CC1NP description
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output polarity
Refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
Refer to CC1E description
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output).
The PWM mode can be used without validating the preload register only in one pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
This bit decreases the latency between a trigger event and a transition on the timer output.
It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output
pulse starting as soon as possible after the starting trigger.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input
is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
set to the compare level independently of the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only
if the channel is configured in PWM1 or PWM2 mode.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
12 11 10 9
Res. Res. Res.
General-purpose timers (TIM15/TIM16/TIM17)
8 7 6
Res. CC2NP Res. CC2P
rw
RM0444 Rev 5
5 4 3 2
CC2E CC1NP CC1NE
rw rw rw rw
1 0
CC1P CC1E
rw rw
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