Rtc Domain Control Register (Rcc_Bdcr) - ST STM32G0 1 Series Reference Manual

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Bits 9:8 FDCANSEL[1:0]: FDCAN clock source selection

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:2 I2S2SEL[1:0]: I2S2 clock source selection

Bits 1:0 I2S1SEL[1:0]: I2S1 clock source selection

RTC domain control register (RCC_BDCR)

Up to three wait states are inserted in case of successive accesses to this register. As this

Power control register 1 (PWR_CR1)

Section 4.1.2: Battery backup of RTC domain on page 120

The register bits are only reset upon RTC domain reset (see

reset), except the LSCOSEL, LSCOEN, and BDRST bits that are only reset upon RTC

domain power-on reset. Any internal or external reset has no effect on these bits.

Address offset: 0x5C

Reset value: 0x0000 0000

This bitfield is controlled by software to select the FDCAN clock as follows:

11: Reserved

This bitfield is controlled by software to select I2S2 clock source as follows:

11: External I2S clock selected as I2S2

This bitfield is controlled by software to select I2S1 clock source as follows:

11: External I2S clock selected as I2S1

domain, it is write-protected upon reset. The DBP bit of the

must be set to allow their modification. Refer to

RM0444 Rev 5

Reset and clock control (RCC)

for further information.

Section 5.1.3: RTC domain

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