Debug Mode; I2C Low-Power Modes; Table 176. Effect Of Low-Power Modes On The I2C - ST STM32G0 1 Series Reference Manual

RM0444
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
•
In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
•
If SMBus is supported (see
managed with the NBYTES counter. Refer to
SMBus Master receiver on page
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
32.4.19

Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT
configuration bits in the DBG module.
32.5

I2C low-power modes

Mode
Sleep
(1)
Stop
Standby
1. Refer to
instance. If wakeup from a specific Stop mode is not supported, the instance must be disabled before
entering this Stop mode.

Table 176. Effect of low-power modes on the I2C

No effect. I2C interrupts cause the device to exit the Sleep mode.
The I2C registers content is kept. If WUPEN = 1 and I2C is clocked by an internal
oscillator (HSI16): the address recognition is functional. The I2C address match
condition causes the device to exit the Stop mode. If WUPEN=0: the I2C must be
disabled before entering Stop mode
The I2C peripheral is powered down and must be reinitialized after exiting
Standby mode.
Section 32.3: I2C implementation
Inter-integrated circuit (I2C) interface
Section 32.3: I2C implementation): the PEC transfer is
SMBus Slave receiver on page 970
974.
Description
for information about the Stop modes supported by each
RM0444 Rev 5
and
979/1390
997