True random number generator (RNG)
19.3
RNG functional description
19.3.1
RNG block diagram
Figure 72
rng_it
rng_clk
19.3.2
RNG internal signals
Table 99
the STM32 product level (on pads).
Signal name
460/1390
shows the RNG block diagram.
Figure 72. RNG block diagram
Banked Registers
control
data
AHB
interface
status
AHB clock domain
RNG clock domain
describes a list of useful-to-know internal signals available at the RNG level, not at
Table 99. RNG internal input/output signals
Signal type
rng_it
Digital output
rng_hclk
Digital input
rng_clk
Digital input
RNG_CR
RNG_DR
RNG_SR
Fault detection
Clock checker
en_osc
RNG global interrupt request
AHB clock
RNG dedicated clock, asynchronous to rng_hclk
RM0444 Rev 5
True RNG
Conditioning logic
128-bit
Raw data shift reg
2-bit
Sampling &
Normalization (x 2)
Analog
Analog
noise
noise
source 1
source 2
Analog noise source
Description
RM0444
MSv42097V2
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