Adc Watchdog Threshold Register (Adc_Awd1Tr) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:8 SMPSEL[18:0] Channel-x sampling time selection
These bits are written by software to define which sampling time is used.
0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 SMP2[2:0]: Sampling time selection 2
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMP1[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
15.12.7

ADC watchdog threshold register (ADC_AWD1TR)

Address offset: 0x20
Reset value: 0x0FFF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
28 27 26 25
rw rw rw
12 11 10 9
rw rw rw
1
24 23 22
HT1[11:0]
rw rw rw
8 7 6
LT1[11:0]
rw rw rw
RM0444 Rev 5
Analog-to-digital converter (ADC)
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
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