Nested Vectored Interrupt Controller (Nvic); Main Features; Systick Calibration Value Register; Interrupt And Exception Vectors - ST STM32G0 1 Series Reference Manual

Nested vectored interrupt controller (NVIC)

12 Nested vectored interrupt controller (NVIC)
12.1

Main features

•
32 maskable interrupt channels (not including the sixteen Cortex
•
4 programmable priority levels (2 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
•
Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the programming manual PM0223.
12.2

SysTick calibration value register

The SysTick calibration value is set to 6500, which gives a reference time base of 1 ms with
the SysTick clock set to 6.5 MHz (max f
12.3

Interrupt and exception vectors

Table 58
containing that peripheral.
Position Priority
- -
- -3
- -2
- -1
- -
- 3
314/1390
is the vector table. Information pertaining to a peripheral only applies to devices

Table 58. Vector table

Type of
Acronym
priority
- -
fixed Reset
fixed NMI_Handler
fixed HardFault_Handler
- -
settable SVC_Handler
/8).
HCLK
(1)
Description
Reserved
Reset
Non maskable interrupt. The SRAM
parity err., Flash ECC double err.,
HSE CSS and LSE CSS are linked
to the NMI vector.
All class of fault
Reserved
System service call via SWI
instruction
RM0444 Rev 5
RM0444
®
-M0+ interrupt lines)
Address
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
0x0000_001C
0x0000_0020
0x0000_0024
0x0000_0028
0x0000_002C