Adc Channel Selection Register [Alternate] (Adc_Chselr) - ST STM32G0 1 Series Reference Manual

RM0444
15.12.9

ADC channel selection register [alternate] (ADC_CHSELR)

Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current
section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in ADC_CFGR1). Refer to
next section.
CHSELRMOD = 0 in ADC_CFGR1:
31 30 29
Res. Res. Res. Res.
15 14 13
CHSEL CHSEL CHSEL CHSEL
15 14 13
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:0 CHSEL[18:0]: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels to
be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or
changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
28 27 26 25
Res. Res. Res.
12 11 10 9
CHSEL CHSEL CHSEL
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
CHSEL CHSEL CHSEL CHSEL
8 7 6
rw rw rw
RM0444 Rev 5
Analog-to-digital converter (ADC)
21 20 19 18
CHSEL
Res. Res. Res.
18
rw
5 4 3 2
CHSEL CHSEL CHSEL
5 4 3 2
rw rw rw rw
17 16
CHSEL CHSEL
17 16
rw rw
1 0
CHSEL CHSEL
1 0
rw rw
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