Tamp Backup X Register (Tamp_Bkpxr) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 CTAMP3F: Clear TAMP3 detection flag
Bit 1 CTAMP2F: Clear TAMP2 detection flag
Bit 0 CTAMP1F: Clear TAMP1 detection flag
31.6.8

TAMP backup x register (TAMP_BKPxR)

Address offset: 0x100 + 0x04 * x, (x = 0 to 4)
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 BKP[31:0]
Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
The application can write or read data to and from these registers.
They are powered-on by V
reset, and their contents remain valid when the device operates in low-power mode.
In the default configuration this register is reset on a tamper detection event. It is forced to
reset value as long as there is at least one internal or external tamper flag being set. This
register is also reset when the readout protection (RDP) is disabled.
Tamper and backup registers (TAMP)
24 23 22
BKP[31:16]
rw rw rw
8 7 6
BKP[15:0]
rw rw rw
when V is switched off, so that they are not reset by System
BAT DD
RM0444 Rev 5
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw w
17 16
rw rw
1 0
rw rw
925/1390
926