Internal Pull-Up & Pull-Down On Swd Pins; Id Codes And Locking Mechanism; Swd Port; Swd Protocol Introduction - ST STM32G0 1 Series Reference Manual

RM0444
40.3.3 Internal pull-up & pull-down on SWD pins
Once the SW I/O is released by the user software, the GPIO controller takes control of these
pins. The reset states of the GPIO control registers put the I/Os in the equivalent states:
•
SWDIO: input pull-up
•
SWCLK: input pull-down
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.
40.4

ID codes and locking mechanism

There are several ID codes inside the MCU. ST strongly recommends the tool
manufacturers (for example Keil, IAR, Raisonance) to lock their debugger using the MCU
device ID located at address 0x40015800.
Only the DEV_ID[15:0] should be used for identification by the debugger/programmer tools
(the revision ID must not be taken into account).
40.5

SWD port

40.5.1

SWD protocol introduction

This synchronous serial protocol uses two pins:
• SWCLK: clock from host to target
•
SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by Arm).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.
40.5.2

SWD protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target
RM0444 Rev 5
Debug support (DBG)
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