General-Purpose I/Os (Gpio); Introduction; Gpio Main Features; Gpio Functional Description - ST STM32G0 1 Series Reference Manual

General-purpose I/Os (GPIO)

7 General-purpose I/Os (GPIO)
7.1

Introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
7.2

GPIO main features

•
Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•
Analog function
•
Alternate function selection registers (at most 8 AFs possible per I/O)
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
7.3

GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
•
Input floating
• Input pull-up
•
Input-pull-down
• Analog
•
Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and
GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR
registers. In this way, there is no risk of an IRQ occurring between the read and the modify
access.
232/1390 RM0444 Rev 5
RM0444