Figure 295. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1; Figure 296. Transfer Bus Diagrams For I2C Slave Receiver - ST STM32G0 1 Series Reference Manual

Inter-integrated circuit (I2C) interface

Figure 295. Transfer sequence flowchart for slave receiver with NOSTRETCH=1

Example I2C slave receiver 3 bytes, NOSTRETCH=0:
RXNE
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: RXNE ISR: rd data1
EV3 : RXNE ISR: rd data2
EV4: RXNE ISR: rd data3
Example I2C slave receiver 3 bytes, NOSTRETCH=1:
RXNE
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
EV4: STOPF ISR: set STOPCF
948/1390
I2C_ISR.RXNE
=1?
Yes
Read I2C_RXDR.RXDATA

Figure 296. Transfer bus diagrams for I2C slave receiver

ADDR
Address data1
A
EV1
RXNE
Address data 1
A
Slave reception
Slave initialization
No
RXNE
RXNE
data2
A A
EV2
RXNE RXNE
data 2 data 3
A A
EV1 EV2
RM0444 Rev 5
No
I2C_ISR.STOPF
=1?
Yes
Set I2C_ICR.STOPCF
RXNE
data3
A
EV3 EV4
A
EV3
RM0444
MS19856V2
legend:
transmission
reception
SCL stretch
legend:
transmission
reception
SCL stretch
MS19857V2