Rng Clocking; Error Management - ST STM32G0 1 Series Reference Manual

RM0444
To run the RNG in polling mode following steps are recommended:
1. Enable the random number generation by setting the RNGEN bit to "1" in the RNG_CR
register.
2. Read the RNG_SR register and check that:
–
–
3. If above conditions are true read the content of the RNG_DR register up to four
consecutive times. If valid data is available in the conditioning output buffer four
additional words can be read by the application (in this case the DRDY bit is still high).
If one or both of above conditions are false, the RNG_DR register must not be read. If
an error occurred error recovery sequence described in
Note: When data is not ready (DRDY="0") RNG_DR returns zero.
It is recommended to always verify that RNG_DR is different from zero. Because when it is
the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare
event).
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in
Software post-processing
If a NIST approved DRBG with 128 bits of security strength is required an approved random
generator software must be built around the RNG true random number generator.
Built-in health check functions are described in
19.3.6

RNG clocking

The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and conditioning component. The
RNG clock is used for noise source sampling. Recommended clock configurations are
detailed in
Note: When the CED bit in the RNG_CR register is set to "0", the RNG clock frequency should be
higher than AHB clock frequency divided by 32, otherwise the clock checker always flags a
clock error (CECS=1 in the RNG_SR register).
See Section 19.3.1: RNG block diagram
19.3.7

Error management

In parallel to random number generation an health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG sets to "1" both the CEIS and CECS bits to indicate that a clock error
occurred. In this case, the application should check that the RNG clock is configured
No error occurred (the SEIS and CEIS bits should be set to 0)
A random number is ready (the DRDY bit should be set to 1)
Section 19.3.8: RNG low-power
Section 19.6: RNG entropy source
True random number generator (RNG)
usage.
Section 19.3.3: Random number
validation.
for details (AHB and RNG clock domains).
RM0444 Rev 5
Section 19.3.7 must be used.
generation.
465/1390
472