Dma Pins And Internal Signals; Dma Transfers; Table 47. Dma Internal Input/Output Signals; Figure 22. Dma Block Diagram - ST STM32G0 1 Series Reference Manual

RM0444
The DMA block diagram is shown in the figure below.
dma_req [1..7]
dma_ack [1..7]
The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.
10.4.2

DMA pins and internal signals

10.4.3

DMA transfers

The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.

Figure 22. DMA block diagram

Ch 1
Ch 2
Ch 7
Arbiter
dma_it[1..7]

Table 47. DMA internal input/output signals

Signal name
dma_req[x]
dma_ack[x]
dma_it[x]
Direct memory access controller (DMA)
DMA
AHB master interface
Interrupt
AHB slave interface
interface
Signal type
Input DMA channel x request
Output DMA channel x acknowledge
Output DMA channel x interrupt
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