Input Capture Mode; Figure 232. Capture/Compare Channel 1 Main Circuit; Figure 233. Output Stage Of Capture/Compare Channel (Channel 1) - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM14)
Input mode
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
CNT > CCR1
CNT = CCR1
1. Available on TIM12 only.
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
24.3.5

Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
724/1390

Figure 232. Capture/compare channel 1 main circuit

APB Bus
MCU-peripheral interface
Capture/compare preload register
Capture
compare shadow register
Counter

Figure 233. Output stage of capture/compare channel (channel 1)

OC1REF
Output
mode
controller
(1)
OC2REF
OC1M[3:0]
TIMx_CCMR1
16/32-bit
Compare
transfer
Comparator
To the master mode
controller
OC1REFC
'0'
0
Output
1
selector
CC1E
TIM1_CCER
RM0444 Rev 5
Output mode
CC1S[1]
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
0 Output
OC1
enable
1 circuit
CC1P CC1E
TIM1_CCER TIM1_CCER
RM0444
OC1PE
TIMx_CCMR1
MSv63030V1
MSv45743V3