Figure 383. Operations Required To Transmit 0X3478Ae; Figure 384. Operations Required To Receive 0X3478Ae; Figure 385. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame - ST STM32G0 1 Series Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
•
In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR
register are required on each RXNE event.
CK
WS
SD
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in
1172/1390

Figure 383. Operations required to transmit 0x3478AE

First write to Data register
conditioned by TXE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.

Figure 384. Operations required to receive 0x3478AE

First read from Data register
conditioned by RXNE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.

Figure 385. LSB justified 16-bit extended to 32-bit packet frame

16-bit data
0 forced
Channel left 32-bit
Figure 386
RM0444 Rev 5
Second write to Data register
conditioned by TXE=1
Second read from Data register
conditioned by RXNE=1
Transmission
16-bit remaining
MSB
is required.
0x78AE
0x78AE
Reception
LSB
Channel right
RM0444
MS19596V1
MS19597V1
MS30105V1