Fdcan Error Counter Register (Fdcan_Ecr); Fdcan Protocol Status Register (Fdcan_Psr) - ST STM32G0 1 Series Reference Manual

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FD controller area network (FDCAN)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TOC[15:0]: Timeout counter

The timeout counter is decremented in multiples of CAN bit times [1 ... 16] depending on the

configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the

Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

FDCAN error counter register (FDCAN_ECR)

Address offset: 0x0040

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 CEL[7:0]: CAN error logging

The counter is incremented each time when a CAN protocol error causes the transmit error

counter or the receive error counter to be incremented. It is reset by read access to CEL. The

counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO].

Access type is RX: reset on read.

Bit 15 RP: Receive error passive

0: The receive error counter is below the error passive level of 128.

1: The receive error counter has reached the error passive level of 128.

Bits 14:8 REC[6:0]: Receive error counter

Actual state of the receive error counter, values between 0 and 127.

Bits 7:0 TEC[7:0]: Transmit error counter

Actual state of the transmit error counter, values between 0 and 255.

When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC

when a CAN protocol error is detected, but CEL is still incremented.

Address offset: 0x0044

Reset value: 0x0000 0707

RM0444 Rev 5

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