Fdcan Extended Id And Mask Register (Fdcan_Xidam); Fdcan High-Priority Message Status Register (Fdcan_Hpms) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 1 RRFS: Reject remote frames standard
0: Filter remote frames with 11-bit standard IDs
1: Reject all remote frames with 11-bit standard IDs
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bit 0 RRFE: Reject remote frames extended
0: Filter remote frames with 29-bit standard IDs
1: Reject all remote frames with 29-bit standard IDs
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
36.4.20

FDCAN extended ID and mask register (FDCAN_XIDAM)

Address offset: 0x0084
Reset value: 0x1FFF FFFF
31 30 29
Res. Res. Res.
15 14 13
rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:0 EIDM[28:0]: Extended ID mask
For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the
Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the
reset value of all bits set to 1 the mask is not active.
These are protected write (P) bits, which means that write access by the bits is possible only
when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
36.4.21

FDCAN high-priority message status register (FDCAN_HPMS)

This register is updated every time a Message ID filter element configured to generate a
priority event match. This can be used to monitor the status of incoming high priority
messages and to enable fast access to these messages.
Address offset: 0x0088
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
FLST Res. Res.
r
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
FIDX[4:0]
r r r r
FD controller area network (FDCAN)
24 23 22
EIDM[28:16]
rw rw rw
8 7 6
EIDM[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
MSI[1:0]
r r r
RM0444 Rev 5
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res.
r
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
BIDX[2:0]
r r
1247/1390
1261