Analog-to-digital converter (ADC)
Raw 20-bit data:
The
Table 76
conversion data equal to 0xFFF.
Table 76. Maximum output results vs N and M. Grayed values indicates truncation
No-shift
Oversa
Max
mpling
OVSS =
Raw data
ratio
2x
0x1FFE
0x1FFE
4x
0x3FFC
0x3FFC
8x
0x7FF8
0x7FF8
16x
0xFFF0
0xFFF0
32x
0x1FFE0
0xFFE0
64x
0x3FFC0
0xFFC0
128x
0x7FF80
0xFF80
256x
0xFFF00
0xFF00
The conversion timings in oversampled mode do not change compared to standard
conversion mode: the sample time is maintained equal during the whole oversampling
sequence. New data are provided every N conversion, with an equivalent delay equal to N x
t
= N x (t
CONV
•
the end of the sampling phase (EOSMP) is set after each sampling phase
•
the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
•
the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)
374/1390
Figure 55. Numerical example with 5-bits shift and rounding
19
3
Final result after 5-bits shift
and rounding to nearest
below gives the data format for the various N and M combination, for a raw
1-bit
2-bit
shift
shift
OVSS =
OVSS =
0000
0001
0010
0x0FFF
0x0800
0x1FFE
0x0FFF
0x3FFC
0x1FFE
0x7FF8
0x3FFC
0xFFF0
0x7FF8
0xFFE0
0xFFF0
0xFFC0
0xFFE0
0xFF80
0xFFC0
+ t
). The flags features are raised as following:
SMPL
SAR
15
11
B
15
1
D
3-bit
4-bit
shift
shift
OVSS =
OVSS =
0011
0100
0x0400
0x0200
0x0800
0x0400
0x0FFF
0x0800
0x1FFE
0x0FFF
0x3FFC
0x1FFE
0x7FF8
0x3FFC
0xFFF0
0x7FF8
0xFFE0
0xFFF0
RM0444 Rev 5
7
3
7
D
B
5-bit
6-bit
shift
shift
OVSS =
OVSS =
OVSS =
0101
0110
0x0100
0x0080
0x0040
0x0200
0x0100
0x0080
0x0400
0x0200
0x0100
0x0800
0x0400
0x0200
0x0FFF
0x0800
0x0400
0x1FFE
0x0FFF
0x0800
0x3FFC
0x1FFE
0x0FFF
0x7FF8
0x3FFC
0x1FFE
RM0444
7
0
F
MS31929V1
7-bit
8-bit
shift
shift
OVSS =
0111
1000
0x0020
0x0040
0x0080
0x0100
0x0200
0x0400
0x0800
0x0FFF
Need help?
Do you have a question about the STM32G0 1 Series and is the answer not in the manual?
Questions and answers