Timx Slave Mode Control Register (Timx_Smcr)(X = 2 To 4) - ST STM32G0 1 Series Reference Manual

RM0444
22.4.3

TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
ETP ECE ETPS[1:0]
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Bits 31:22 Reserved, must be kept at reset value.
Bits 19:17 Reserved, must be kept at reset value.
Bit 15 ETP: External trigger polarity
Bit 14 ECE: External clock enable
Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
Bits 13:12 ETPS[1:0]: External trigger prescaler
28 27 26 25
Res. Res. Res.
12 11 10 9
ETF[3:0]
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This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
connected to ETRF (SMS=111 and TS=00111).
It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 00111).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
General-purpose timers (TIM2/TIM3/TIM4)
24 23 22
Res. Res. Res.
8 7 6
MSM TS[2:0]
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RM0444 Rev 5
21 20 19 18
TS[4:3] Res. Res.
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5 4 3 2
OCCS
rw rw rw rw
17 16
Res. SMS[3]
rw
1 0
SMS[2:0]
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