Adc Configuration Register 1 (Adc_Cfgr1) - ST STM32G0 1 Series Reference Manual

RM0444
15.12.4

ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. AWD1CH[4:0]
rw rw
15 14 13
AUTOFF WAIT CONT OVRMOD
rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWD1CH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
10010: ADC analog input Channel 18 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWD1EN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog 1 disabled
1: Analog watchdog 1 enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
Bit 22 AWD1SGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
28 27 26 25
Res.
rw rw rw
12 11 10 9
EXTEN[1:0] Res.
rw rw rw
register.
The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
ensures that no conversion is ongoing).
ensures that no conversion is ongoing).
24 23 22
AWD1E AWD1SG
Res.
N L
rw rw
8 7 6
EXTSEL[2:0]
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RM0444 Rev 5
Analog-to-digital converter (ADC)
21 20 19 18
CHSEL
Res. Res. Res.
RMOD
rw
5 4 3 2
SCAND
ALIGN RES[1:0]
IR
rw rw rw rw
17 16
Res. DISCEN
rw
1 0
DMAC
DMAEN
FG
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387/1390
403