Iwdg Prescaler Register (Iwdg_Pr) - ST STM32G0 1 Series Reference Manual

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Independent watchdog (IWDG)

IWDG prescaler register (IWDG_PR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PR[2:0]: Prescaler divider

Note: Reading this register returns the prescaler value from the V

These bits are write access protected see

are written by software to select the prescaler divider feeding the counter clock. PVU bit of

IWDG status register (IWDG_SR)

prescaler divider.

000: divider /4

001: divider /8

010: divider /16

011: divider /32

100: divider /64

101: divider /128

110: divider /256

111: divider /256

value may not be up to date/valid if a write operation to this register is ongoing. For this

reason the value read from this register is valid only when the PVU bit in the

status register (IWDG_SR)

Section 28.3.4: Register access

must be reset in order to be able to change the

RM0444 Rev 5

voltage domain. This

protection. They

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