I2C Interrupt Clear Register (I2C_Icr) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 2 RXNE: Receive data register not empty (receivers)
Note: This bit is cleared by hardware when PE=0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
Note: This bit is cleared by hardware when PE=0.
Bit 0 TXE: Transmit data register empty (transmitters)
Note: This bit is set by hardware when PE=0.
32.7.8

I2C interrupt clear register (I2C_ICR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states
31 30 29
Res. Res. Res. Res.
15 14 13
ALERT TIMOU
Res. Res.
CF TCF
w
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 ALERTCF: Alert flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 12 TIMOUTCF: Timeout detection flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 11 PECCF: PEC Error flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
This bit is set by hardware when the received data is copied into the I2C_RXDR register, and
is ready to be read. It is cleared when I2C_RXDR is read.
This bit is set by hardware when the I2C_TXDR register is empty and the data to be
transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be
sent is written in the I2C_TXDR register.
This bit can be written to '1' by software when NOSTRETCH=1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
data to be sent is written in the I2C_TXDR register.
This bit can be written to '1' by software in order to flush the transmit data register
I2C_TXDR.
28 27 26 25
Res. Res. Res.
12 11 10 9
ARLOC
PECCF OVRCF
F
w w w w
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
Refer to Section 32.3: I2C
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.
Refer to Section 32.3: I2C
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.
Refer to Section 32.3: I2C
Inter-integrated circuit (I2C) interface
24 23 22
Res. Res. Res.
8 7 6
BERRC STOPC
Res. Res.
F
w
implementation.
implementation.
implementation.
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
NACKC ADDR
Res.
F F CF
w w w
17 16
Res. Res.
1 0
Res. Res.
993/1390
997