Fdcan Test Register (Fdcan_Test); Fdcan Ram Watchdog Register (Fdcan_Rwd) - ST STM32G0 1 Series Reference Manual

RM0444
36.4.4

FDCAN test register (FDCAN_TEST)

Write access to the Test register has to be enabled by setting bit CCCR[TEST] to 1. All Test
register functions are set to their reset values when bit CCCR[TEST] is reset.
Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes.
Programming TX differently from 00 may disturb the message transfer on the CAN bus.
Address offset: 0x0010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 RX: Receive pin
Monitors the actual value of pin FDCANx_RX
0: The CAN bus is dominant (FDCANx_RX = 0)
1: The CAN bus is recessive (FDCANx_RX = 1)
Bits 6:5 TX[1:0]: Control of transmit pin
00: Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the
CAN bit time
01: Sample point can be monitored at pin FDCANx_TX
10: Dominant (0) level at pin FDCANx_TX
11: Recessive (1) at pin FDCANx_TX
Bit 4 LBCK: Loop back mode
0: Reset value, Loop Back mode is disabled
1: Loop Back mode is enabled (see
Bits 3:0 Reserved, must be kept at reset value.
36.4.5

FDCAN RAM watchdog register (FDCAN_RWD)

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM
access starts the Message RAM Watchdog Counter with the value configured by the
RWD[WDC] bits.
The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful
completion by activating its READY output. In case there is no response from the Message
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
FD controller area network (FDCAN)
24 23 22
Res. Res. Res.
8 7 6
Res. RX TX[1:0]
r rw
Power down (Sleep
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
LBCK Res. Res.
rw rw
mode))
17 16
Res. Res.
1 0
Res. Res.
1229/1390
1261