Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd); Dual Dac 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12Ld) - ST STM32G0 1 Series Reference Manual

RM0444
16.7.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
16.7.10

Dual DAC 12-bit left aligned data holding register

(DAC_DHR12LD)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
Bits 3:0 Reserved, must be kept at reset value.
27 26 25
rw rw rw
11 10 9
rw rw rw
These bits are written by software which specifies 12-bit data for DAC channel2.
These bits are written by software which specifies 12-bit data for DAC channel1.
28 27 26 25
DACC2DHR[11:0]
rw rw rw rw
12 11 10 9
DACC1DHR[11:0]
rw rw rw rw
These bits are written by software which specifies 12-bit data for DAC channel2.
These bits are written by software which specifies 12-bit data for DAC channel1.
24 23 22
DACC2DHR[11:0]
rw rw rw
8 7 6
DACC1DHR[11:0]
rw rw rw
24 23 22
rw rw rw
8 7 6
rw rw rw
RM0444 Rev 5
Digital-to-analog converter (DAC)
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res.
rw rw
5 4 3 2
Res. Res.
rw rw
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
Res. Res.
431/1390
441