Table 244. Txerr Timing Parameters; Figure 423. Txerr Detection - ST STM32G0 1 Series Reference Manual

RM0444
Legend:
T s
Time
T
s
T
1
T
n1
T
2
T
ns
T
3
T
n0
T
4
T
5
T
nf

Figure 423. TXERR detection

TXERR Checking Window
Tx data bit-1
T 1 T n1 T 2 T ns

Table 244. TXERR timing parameters

RXTOL
x
1
0
x
0
1
x 1.05
1
0
x
0
1
1 1.85
0 2.05
x
RM0444 Rev 5
CEC initiator bit-timing
Tx acknowledge
Tx arbitration bit-1
T 3 T n0 T 4
Tx arbitration bit-0
Tx data bit-0
ms
0 Bit start event.
0.3
The earliest time for a low - high transition when
indicating a logical 1.
0.4
The nominal time for a low - high transition when
0.6
indicating a logical 1.
0.8
The latest time for a low - high transition when
indicating a logical 1.
0.9
Nominal sampling time.
1.2
The earliest time a device is permitted return to a
high impedance state (logical 0).
1.3
The nominal time a device is permitted return to a
1.5
high impedance state (logical 0).
1.7
The latest time a device is permitted return to a high
impedance state (logical 0).
1.8
The earliest time for the start of a following bit.
2.4 The nominal data bit period.
HDMI-CEC controller (CEC)
Tolerance margins
T 5 T nf T 6
MS31012V1
Description
1355/1390
1364