Fdcan Transmitter Delay Compensation Register (Fdcan_Tdcr); Fdcan Interrupt Register (Fdcan_Ir) - ST STM32G0 1 Series Reference Manual

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FDCAN transmitter delay compensation register (FDCAN_TDCR)

Address offset: 0x0048

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:8 TDCO[6:0]: Transmitter delay compensation offset

Offset value defining the distance between the measured delay from FDCAN_TX to

FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq.

These are protected write (P) bits, which means that write access by the bits is possible only

when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 TDCF[6:0]: Transmitter delay compensation filter window length

Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would

result in an earlier SSP position are ignored for transmitter delay measurements.

These are protected write (P) bits, which means that write access by the bits is possible only

when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags

remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit

Writing a 0 has no effect. A hard reset clears the register. The configuration of IE controls

whether an interrupt is generated. The configuration of ILS controls on which interrupt line

an interrupt is signaled.

Address offset: 0x0050

Reset value: 0x0000 0000

FD controller area network (FDCAN)

RM0444 Rev 5

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