Figure 395. Transceiver Delay Measurement - ST STM32G0 1 Series Reference Manual

FD controller area network (FDCAN)
m_ttcan_tx
m_ttcan_rx
m_ttcan_cclk
TDCR.TDCO
To avoid that a dominant glitch inside the received FDF bit ends the delay compensation
measurement before the falling edge of the received res bit (resulting in a to early SSP
position), the use of a transmitter delay compensation filter window can be enabled by
programming TDCR.TDCF. This defines a minimum value for the SSP position. Dominant
edges on FDCAN_RX, that would result in an earlier SSP position are ignored for
transmitter delay measurement. The measurement is stopped when the SSP position is at
least TDCR.TDCF and FDCAN_RX is low.
Restricted Operation mode
In Restricted Operation mode the node is able to receive data and remote frames and to
give acknowledge to valid frames, but it does not send data frames, remote frames, active
error frames, or overload frames. In case of an error condition or overload condition, it does
not send dominant bits, instead it waits for the occurrence of bus idle condition to
resynchronize itself to the CAN communication. The error counters (ECR.REC, ECR.TEC)
are frozen while Error Logging (ECR.CEL) is active. The software can set the FDCAN into
Restricted Operation mode by setting bit CCCR.ASM. The bit can only be set by software
when both CCCR.CCE and CCCR.INIT are set to 1. The bit can be cleared by software at
any time.
Restricted Operation mode is automatically entered when the Tx Handler was not able to
read data from the Message RAM in time. To leave Restricted Operation Mode, the software
has to reset CCCR.ASM.
The Restricted Operation mode can be used in applications that adapt themselves to
different CAN bit rates. In this case the application tests different bit rates and leaves the
Restricted Operation mode after it has received a valid frame.
Note: The Restricted Operation mode must not be combined with the Loop Back mode (internal or
external).
1206/1390

Figure 395. Transceiver delay measurement

Transmitter
delay
FDF Res.
Arbitration phase
Arbitration phase
Start Stop
Delay counter
Delay compensation offset
RM0444 Rev 5
BRS DLC
Delay
+
RM0444
Data phase
Data phase
SSP position
MS41483V1