Ucpd Interrupts; Table 240. Ucpd Interrupt Requests - ST STM32G0 1 Series Reference Manual

USB Type-C™ / USB Power Delivery interface (UCPD)
It order to function correctly with the RCC, the clock request signal is activated (conditional
on WUPEN) when there is asynchronous activity on:
•
Type-C voltage threshold detectors (coming from either CC line)
•
Power Delivery receiver signal (from the selected CC line)
•
FRS detection signal (from the selected CC line)
38.6

UCPD interrupts

The table below lists the UCPD event flags, with the associated flag clear bits and interrupt
enable bits.
Type C voltage level change on CC2
Type C voltage level change on CC1
Rx message received
Rx Hard Reset detected
Rx ordered set (4 K-codes) detected
Receive data register not empty
Hard Reset discarded
Transmit message aborted
Transmit message sent
Transmit message discarded
Transmit data required
When an interrupt from the UCPD is received, then the software has to check what is the
source of the interrupt by reading the UCPD_SR register.
Depending on which bit is at 1, the ISR must handle that condition and clear the bit by a
write to the appropriate bit of the UCPD_ICR register.
1328/1390

Table 240. UCPD interrupt requests

Interrupt event
FRS detection
Rx data overflow
Tx data underrun
Hard Reset sent
Event flag/Interrupt
Event flag
FRSEVT
TYPECEVT2 Set TYPECEVT2CF
TYPECEVT1 Set TYPECEVT1CF
RXMSGEND Set RXMSGENDCF
RXOVR
RXHRSTDET Set RXHRSTDETCF
RXORDDET Set RXORDDETCF
RXNE
TXUND
HRSTSENT Set HRSTSENTCF
HRSTDISC
TXMSGABT Set TXMSGABTCF
TXMSGSENT Set TXMSGSENTCF
TXMSGDISC Set TXMSGDISCCF
TXIS
UCPD_TXDR register
RM0444 Rev 5
Interrupt enable
clearing method
Set FRSEVTCF
Set RXOVRCF
Read data in
UCPD_RXDR
Set TXUNDCF
Set HRSTDISCCF
Write data to the
RM0444
control bit
FRSEVTIE
TYPECEVT2IE
TYPECEVT1IE
RXMSGENDIE
RXOVR
RXHRSTDETIE
RXORDDETIE
RXNEIE
TXUNDIE
HRSTSENTIE
HRSTDISCIE
TXMSGABTIE
TXMSGSENTIE
TXMSGDISCIE
TXISIE