Can Rx Fifo 0 Acknowledge Register (Fdcan_Rxf0A); Fdcan Rx Fifo 1 Status Register (Fdcan_Rxf1S) - ST STM32G0 1 Series Reference Manual

Table of Contents

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 F0FL[3:0]: Rx FIFO 0 fill level

Number of elements stored in Rx FIFO 0, range 0 to 3.

CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A)

Address offset: 0x0094

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 F0AI[2:0]: Rx FIFO 0 acknowledge index

After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to

write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx

FIFO 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL].

Address offset: 0x0098

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 RF1L: Rx FIFO 1 message lost

This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset.

0: No Rx FIFO 1 message lost

1: Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0

Bit 24 F1F: Rx FIFO 1 full

0: Rx FIFO 1 not full

1: Rx FIFO 1 full

Bits 23:18 Reserved, must be kept at reset value.

FD controller area network (FDCAN)

RM0444 Rev 5

Show Quick Links

Table of Contents

Do you have a question about the STM32G0 1 Series and is the answer not in the manual?