Debug Support (Dbg); Overview; Figure 424. Block Diagram Of Stm32G0X1 Mcu And Cortex - ST STM32G0 1 Series Reference Manual

RM0444
40

Debug support (DBG)

40.1

Overview

The STM32G0x1 devices are built around a Cortex
extensions for advanced debugging features. The debug extensions allow the core to be
stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When
stopped, the core's internal state and the system's external state may be examined. Once
examination is complete, the core and the system may be restored and program execution
resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32G0x1 MCUs.
One interface for debug is available:
•
Serial wire

Figure 424. Block diagram of STM32G0x1 MCU and Cortex

SWDIO
SWCLK
1. The debug features embedded in the Cortex
The Arm Cortex
•
SW-DP: Serial wire
• BPU: Break point unit
•
DWT: Data watchpoint trigger
STM32 MCU debug suppo rt
Cortex-M0 debug support
Cortex-M0
Core
SW-DP
Debug AP
®
-M0+ core provides integrated on-chip debug support. It is comprised of:
RM0444 Rev 5
®
-M0+ core which contains hardware
Bus matrix
Debug AP
Bridge
NVIC
DWT
BPU
®
-M0+ core are a subset of the Arm CoreSight Design Kit.
Debug support (DBG)
®
-M0+-level debug support
System
interface
DBGMCU
MS19240V2
1365/1390
1378