Rs232 Hardware Flow Control And Rs485 Driver Enable; Figure 350. Hardware Flow Control Between 2 Lpuarts; Figure 351. Rs232 Rts Flow Control - ST STM32G0 1 Series Reference Manual

RM0444
enable bit (EIE bit in the LPUART_CR3 register), which, if set, enables an interrupt after the
current byte if any of these errors occur.
34.4.13

RS232 Hardware flow control and RS485 Driver Enable

It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the LPUART_CR3 register).
RS232 RTS flow control
If the RTS flow control is enabled (RTSE = 1), then nRTS is asserted (tied low) as long as
the LPUART receiver is ready to receive a new data. When the receive register is full, nRTS
is deasserted, indicating that the transmission is expected to stop at the end of the current
frame. Figure 351
RX
nRTS
Note: When FIFO mode is enabled, nRTS is deasserted only when RXFIFO is full.
Low-power universal asynchronous receiver transmitter (LPUART)
Figure 336 shows how to connect 2 devices in this mode:

Figure 350. Hardware flow control between 2 LPUARTs

LPUART 1
TX
TX circuit
CTS
RX
RX circuit
RTS
shows an example of communication with RTS flow control enabled.

Figure 351. RS232 RTS flow control

Start
Data 1
bit
RM0444 Rev 5
RX
RTS
TX
CTS
Stop Start
Idle
bit bit
RXNE
Data 1 read
Data 2 can now be transmitted
LPUART 2
RX circuit
TX circuit
MSv31892V2
Stop
Data 2
bit
RXNE
MSv31168V1
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