Ahb Peripheral Clock Enable In Sleep/Stop Mode Register (Rcc_Ahbsmenr) - ST STM32G0 1 Series Reference Manual

RM0444
15 14 13
Res. Res. Res. Res.
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to
Section 1.4: Availability of
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFSMEN: I/O port F clock enable during Sleep mode
Bit 4 GPIOESMEN: I/O port E clock enable during Sleep mode
Bit 3 GPIODSMEN: I/O port D clock enable during Sleep mode
Bit 2 GPIOCSMEN: I/O port C clock enable during Sleep mode
Bit 1 GPIOBSMEN: I/O port B clock enable during Sleep mode
Bit 0 GPIOASMEN: I/O port A clock enable during Sleep mode
5.4.18 AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR)
Address offset: 0x48
Reset value: 0x0005 1303
12 11 10 9
Res. Res. Res.
peripherals.
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
8 7 6
GPIOF
Res. Res. Res.
SMEN
RM0444 Rev 5
Reset and clock control (RCC)
5 4 3 2
GPIOE
GPIOD GPIOC
SMEN
SMEN SMEN
(1)
rw rw rw rw
(1)
1 0
GPIOB GPIOA
SMEN SMEN
rw rw
203/1390
220