Lptim Implementation; Lptim Functional Description; Lptim Block Diagram; Table 131. Stm32G0X1 Lptim Features - ST STM32G0 1 Series Reference Manual

Low-power timer (LPTIM)
26.3

LPTIM implementation

Table 131
is implemented in LPTIM1. LPTIM2 supports a smaller set of features, but is otherwise
identical to LPTIM1.
Encoder mode
1. X = supported.
26.4

LPTIM functional description

26.4.1

LPTIM block diagram

Figure 270. Low-power timer block diagram (LPTIM1 and LPTIM2

LPTIM
lptim_pclk
clock domain
LPTIM
register
interface
lptim_pclk
IRQ
lptim_it
interface
lptim_
ker_ck
lptim_
wkup
1. LPTIM2 has only the input channel 1, no input channel 2
2. lptim_out is the internal LPTIM output signal that can be connected to internal peripherals.
832/1390
describes LPTIM implementation on STM32G0x1 devices: the full set of features

Table 131. STM32G0x1 LPTIM features

LPTIM modes/features
Up/down
Encoder
1
CLKMUX
0
(1)
lptim_ker_ck clock domain
CNTSTRT/
Glitch
SNGSTRT
filter
16-bit ARR
Mux trigger
1
1 0
16-bit counter
Count
mode
Prescaler
16-bit compare
RM0444 Rev 5
LPTIM1 LPTIM2
X
(1)
)
lptim_in2_mux1
lptim_in2_mux2
Glitch
lptim_in2_mux3
filter
LPTIM_IN2
lptim_in1_mux1
lptim_in1_mux2
Glitch lptim_in1_mux3
filter
LPTIM_IN1
lptim_ext_trigx
LPTIM_ETR
LPTIM_OUT
lptim_out
RM0444
-
(2)
MSv47463V1