Dbg Register Map - ST STM32G0 1 Series Reference Manual

RM0444
31 30 29 28
15 14 13 12
rw
1. Only significant on devices integrating TIM15, otherwise reserved. Refer to
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: Clocking of TIM17 counter when the core is halted
This bit enables/disables the clock to the counter of TIM17 when the core is halted:
0: Enable
1: Disable
Bit 17 DBG_TIM16_STOP: Clocking of TIM16 counter when the core is halted
This bit enables/disables the clock to the counter of TIM16 when the core is halted:
0: Enable
1: Disable
Bit 16 DBG_TIM15_STOP: Clocking of TIM15 counter when the core is halted
This bit enables/disables the clock to the counter of TIM15 when the core is halted:
0: Enable
1: Disable
Bit 15 DBG_TIM14_STOP: Clocking of TIM14 counter when the core is halted
This bit enables/disables the clock to the counter of TIM14 when the core is halted:
0: Enable
1: Disable
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: Clocking of TIM1 counter when the core is halted
This bit enables/disables the clock to the counter of TIM1 when the core is halted:
0: Enable
1: Disable
Bits 10:0 Reserved, must be kept at reset value.
40.10.5

DBG register map

The following table summarizes the Debug registers.
27 26 25 24
11 10 9 8
rw
RM0444 Rev 5
23 22 21 20
7 6 5 4
Section 1.4: Availability of peripherals
Debug support (DBG)
19 18 17
rw rw
3 2 1
1377/1390
16
rw
0
1378