Clock Selection - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM14)
Figure 229. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload shadow
Write a new value in TIMx_ARR
24.3.3

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
Internal clock source (CK_INT)
The internal clock source is the default clock source for TIM14.
Figure 230
without prescaler.
722/1390
CK_PSC
CEN
F0
(UIF)
F5
register
register
shows the behavior of the control circuit and the upcounter in normal mode,
RM0444 Rev 5
preloaded)
F1 F2 F3 F4 F5 00
F5
01 02 03 04 05 06 07
36
36
RM0444
MS31083V2