Figure 87. Ecb/Cbc Encryption (Mode 1) - ST STM32G0 1 Series Reference Manual

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The second ciphertext block is processed in the same way as the first block, except that the
I1 data from the first block is used in place of the initialization vector.
The decryption continues in this way until the last complete ciphertext block is decrypted.
If the message size is not a multiple of 128 bits, the final partial data block is decrypted in
the way explained in
For more information on data swapping, refer to
data swapping.
ECB/CBC encryption sequence
The sequence of events to perform an ECB/CBC encryption (more detail in
1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. Select the Mode 1 by setting to 00 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR
register to 000 or 001, respectively. Data type can also be defined, using
DATATYPE[1:0] bitfield.
3. Select 128- or 256-bit key length through the KEYSIZE bit of the AES_CR register.
4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Fill the
AES_IVRx registers with the initialization vector data if CBC mode has been selected.
5. Enable the AES peripheral by setting the EN bit of the AES_CR register.
6. Write the AES_DINR register four times to input the plaintext (MSB first), as shown in
Figure
7. Wait until the CCF flag is set in the AES_SR register.
8. Read the AES_DOUTR register four times to get the ciphertext (MSB first) as shown in
Figure
9. Repeat steps
WR
PT3
MSB
4 write operations into
AES_DINR[31:0]
PT = plaintext = 4 words (PT3, ... , PT0)
CT = ciphertext = 4 words (CT3, ... , CT0)
ECB/CBC decryption sequence
The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail
in Section
1. Follow the steps described in
order to prepare the decryption key in AES core.
2. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR
Section 20.4.6: AES ciphertext stealing and data
87.
87. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
6-7-8 to process all the blocks with the same encryption key.

Figure 87. ECB/CBC encryption (Mode 1)

WR WR WR
PT2 PT1 PT0
LSB
Input phase
20.4.4).
Section 20.4.13: AES data registers and
Wait until flag CCF = 1
Computation phase
Section 20.4.5: AES decryption round key
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AES hardware accelerator (AES)
padding.
Section
RD RD
CT3 CT2 CT1
MSB
Output phase
4 read operations of
AES_DOUTR[31:0]
preparation, in
20.4.4):
RD RD
CT0
LSB
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