Figure 60. Data Registers In Single Dac Channel Mode; Figure 61. Data Registers In Dual Dac Channel Mode - ST STM32G0 1 Series Reference Manual

RM0444
•
Dual DAC channels (when available)
There are three possibilities:
–
–
–
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-
mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1
and DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.

Figure 60. Data registers in single DAC channel mode

31 24
8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD
[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded
into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD
[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be
loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
12-bit right alignment: data for DAC channel1 to be loaded into the
DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC
channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored into the
DHR2[11:0] bits)

Figure 61. Data registers in dual DAC channel mode

31 24
15 7
15 7
RM0444 Rev 5
Digital-to-analog converter (DAC)
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710b
ai14709b
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