Figure 50. Adc_Awdx_Out Signal Generation; Figure 51. Adc_Awdx_Out Signal Generation (Awdx Flag Not Cleared By Software) - ST STM32G0 1 Series Reference Manual

RM0444
The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the
comparison.
As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.
ADC STATE
RDY
EOC FLAG
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

Figure 51. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software)

ADC STATE RDY
EOC FLAG
AWDx FLAG
ADC_AWDx_OUT
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

Figure 50. ADC_AWDx_OUT signal generation

Conversion1 Conversion2
inside outside
Conversion1 Conversion2
inside outside
Conversion3 Conversion4
inside outside
Cleared
by SW
Conversion3 Conversion4
inside outside
not cleared by SW
RM0444 Rev 5
Analog-to-digital converter (ADC)
Conversion5 Conversion6
outside outside
Cleared Cleared
by SW by SW
Conversion5 Conversion6
outside outside
Conversion7
inside
Cleared
by SW
MSv45362V1
Conversion7
inside
MSv45363V1
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