Comparator 2 Control And Status Register (Comp2_Csr) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 11 WINMODE: Comparator 1 non-inverting input selector for window mode
Bit 10 Reserved, must be kept at reset value
Bits 9:8 INPSEL[1:0]: Comparator 1 signal selector for non-inverting input
Bits 7:4 INMSEL[3:0]: Comparator 1 signal selector for inverting input INM
Bits 3:1 Reserved, must be kept at reset value
Bit 0 EN: Comparator 1 enable bit
18.6.2

Comparator 2 control and status register (COMP2_CSR)

Address offset: 0x04
System reset value: 0x0000 0000
31 30 29
LOCK VALUE Res.
rw r
15 14 13
POLARITY WINOUT Res.
rw rw
This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of
the comparator 1:
0: Signal selected with INPSEL[1:0] bitfield of this register
1: COMP2_INP signal of the comparator 2 (required for window mode, see
This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting
input COMP1_INP of the comparator 1 (also see the WINMODE bit):
00: PC5
01: PB2
10: PA1
11: None (open)
This bitfield is controlled by software (if not locked). It selects the signal for the inverting
input COMP1_INM of the comparator 1:
0000: 1/4 V
REFINT
0001: 1/2 V
REFINT
0010: 3/4 V
REFINT
0011: V
REFINT
0100: DAC channel 1
0101: DAC channel 2
0110: PB1
0111: PC4
1000: PA0
> 1000: 1/4 V
REFINT
This bit is controlled by software (if not locked). It enables the comparator 1:
0: Disable
1: Enable
28 27 26
Res. Res. Res.
12 11 10
Res. WINMODE Res.
rw
25 24 23 22
Res. BLANKSEL
rw rw rw
9 8 7 6
INPSEL INMSEL
rw rw rw rw
RM0444 Rev 5
Comparator (COMP)
Figure
21 20 19 18
PWRMODE
rw rw rw rw
5 4 3 2
Res. Res.
rw rw
69)
17 16
HYST
rw rw
1 0
Res. EN
rw
453/1390
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