Figure 195. Clearing Timx Ocxref - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4)
The OCxREF signal for a given channel can be reset by applying a high level on the ETRF
input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF
remains low until the next update event (UEV) occurs.
This function can be used only in the output compare and PWM modes. It does not work in
forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be
used for current handling. In this case, ETR must be configured as follows:
1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.
2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is
cleared to 0.
3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application's needs.
Figure 195
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.
Counter (CNT)
(OCxCE = '0')
(OCxCE = '1')
Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the
next counter overflow.
654/1390
shows the behavior of the OCxREF signal when the ETRF input becomes high,

Figure 195. Clearing TIMx OCxREF

(CCRx)
ETRF
OCxREF
OCxREF
ocref_clr_int ocref_clr_int
becomes high
RM0444 Rev 5
still high
RM0444
MS33105V2