Figure 191. Edge-Aligned Pwm Waveforms (Arr=8) - ST STM32G0 1 Series Reference Manual

RM0444
cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:
•
When the result of the comparison or
•
When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the "frozen" configuration (no comparison, OCxM='000) to one of the PWM modes
(OCxM='110 or '111).
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
mode on page
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at '1.
If the compare value is 0 then OCxREF is held at '0.
PWM waveforms in an example where TIMx_ARR=8.
CCRx=4
CCRx=8
CCRx>8
CCRx=0
629.

Figure 191. Edge-aligned PWM waveforms (ARR=8)

Counter register 0
OCXREF
CCxIF
OCXREF
CCxIF
'1'
OCXREF
CCxIF
OCXREF '0'
CCxIF
General-purpose timers (TIM2/TIM3/TIM4)
Figure 191
1 2 3 4 5
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Upcounting
shows some edge-aligned
6 7 8 0 1
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