Ucpd Status Register (Ucpd_Sr) - ST STM32G0 1 Series Reference Manual

USB Type-C™ / USB Power Delivery interface (UCPD)
Bit 6 TXUNDIE: TXUND interrupt enable
0: Disable
1: Enable
Bit 5 HRSTSENTIE: HRSTSENT interrupt enable
0: Disable
1: Enable
Bit 4 HRSTDISCIE: HRSTDISC interrupt enable
0: Disable
1: Enable
Bit 3 TXMSGABTIE: TXMSGABT interrupt enable
0: Disable
1: Enable
Bit 2 TXMSGSENTIE: TXMSGSENT interrupt enable
0: Disable
1: Enable
Bit 1 TXMSGDISCIE: TXMSGDISC interrupt enable
0: Disable
1: Enable
Bit 0 TXISIE: TXIS interrupt enable
0: Disable
1: Enable
38.7.6

UCPD status register (UCPD_SR)

Address offset: 0x014
Reset value: 0x0000 0000
The flags (single-bit status bitfields) are associated with interrupt request. Interrupt is
generated if enabled by the corresponding bit of the UCPD_IMR register.
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
1336/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
24 23 22
Res. Res. Res.
8 7 6
RXNE Res.
r r
RM0444 Rev 5
21 20 19 18
Res.
r r r
5 4 3 2
r r r r
RM0444
17 16
r r
1 0
TXIS
r r