Apb Peripheral Reset Register 2 (Rcc_Apbrstr2) - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
Bit 12 FDCAN: FDCAN reset
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 USART6RST: USART3 reset
Bit 8 USART5RST: USART3 reset
Bit 7 LPUART2RST: LPUART2 reset
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: TIM7 timer reset
Bit 4 TIM6RST: TIM6 timer reset
Bit 3 Reserved, must be kept at reset value.
Bit 2 TIM4RST: TIM3 timer reset
Bit 1 TIM3RST: TIM3 timer reset
Bit 0 TIM2RST: TIM2 timer reset
5.4.12

APB peripheral reset register 2 (RCC_APBRSTR2)

Address offset: 0x30
Reset value: 0x0000 0000
194/1390
(1)
Set and cleared by software.
0: No effect
1: Reset FDCAN
Set and cleared by software.
0: No effect
1: Reset USART6
Set and cleared by software.
0: No effect
1: Reset USART5
Set and cleared by software.
0: No effect
1: Reset LPUART2
Set and cleared by software.
0: No effect
1: Reset TIM7
Set and cleared by software.
0: No effect
1: Reset TIM6
Set and cleared by software.
0: No effect
1: Reset TIM4
Set and cleared by software.
0: No effect
1: Reset TIM3
Set and cleared by software.
0: No effect
1: Reset TIM2
(1)
(1)
(1)
(1)
(1)
(1)
RM0444 Rev 5
RM0444